/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_GPIO_HW_H
#define RK_GPIO_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the GPIO.
 */
#define RK_GPIO_SWPORT_DR_L_OFFSET      0x0000U /* Port Data Register (Low) */
#define RK_GPIO_SWPORT_DR_H_OFFSET      0x0004U /* Port Data Register (High) */
#define RK_GPIO_SWPORT_DDR_L_OFFSET     0x0008U /* Port Data Direction Register (Low) */
#define RK_GPIO_SWPORT_DDR_H_OFFSET     0x000CU /* Port Data Direction Register (High) */
#define RK_GPIO_INT_EN_L_OFFSET         0x0010U /* Interrupt Enable Register (Low) */
#define RK_GPIO_INT_EN_H_OFFSET         0x0014U /* Interrupt Enable Register (High) */
#define RK_GPIO_INT_MASK_L_OFFSET       0x0018U /* Interrupt Mask Register (Low) */
#define RK_GPIO_INT_MASK_H_OFFSET       0x001CU /* Interrupt Mask Register (High) */
#define RK_GPIO_INT_TYPE_L_OFFSET       0x0020U /* Interrupt Type Register (Low) */
#define RK_GPIO_INT_TYPE_H_OFFSET       0x0024U /* Interrupt Type Register (High) */
#define RK_GPIO_INT_POLARITY_L_OFFSET   0x0028U /* Interrupt Polarity Register (Low) */
#define RK_GPIO_INT_POLARITY_H_OFFSET   0x002CU /* Interrupt Polarity Register (High) */
#define RK_GPIO_INT_BOTHEDGE_L_OFFSET   0x0030U /* Interrupt Both Edge Type Register (Low) */
#define RK_GPIO_INT_BOTHEDGE_H_OFFSET   0x0034U /* Interrupt Both Edge Type Register (High) */
#define RK_GPIO_DEBOUNCE_L_OFFSET       0x0038U /* Debounce Enable Register (Low) */
#define RK_GPIO_DEBOUNCE_H_OFFSET       0x003CU /* Debounce Enable Register (High) */
#define RK_GPIO_DBCLK_DIV_EN_OFFSET     0x0040U /* DBCLK Divide Enable Register (Low) */
#define RK_GPIO_DBCLK_DIV_EN_OFFSET     0x0044U /* DBCLK Divide Enable Register (High) */
#define RK_GPIO_DBCLK_DIV_CON_OFFSET    0x0048U /* DBCLK Divide Control Register */
#define RK_GPIO_INT_STATUS_OFFSET       0x0050U /* Interrupt Status Register */
#define RK_GPIO_INT_RAWSTATUS_OFFSET    0x0058U /* Interrupt Raw Status Register */
#define RK_GPIO_PORT_EOI_L_OFFSET       0x0060U /* Interrupt Clear Register (Low) */
#define RK_GPIO_PORT_EOI_H_OFFSET       0x0064U /* Interrupt Clear Register (High) */
#define RK_GPIO_EXT_PORT_OFFSET         0x0070U /* External Port Data Register */
#define RK_GPIO_VER_ID_OFFSET           0x0078U /* Version ID Register */
#define RK_GPIO_REG_GROUP_L_OFFSET      0x0100U /* GPIO Group Control Register (Low) */
#define RK_GPIO_REG_GROUP_H_OFFSET      0x0104U /* GPIO Group Control Register (High) */
#define RK_GPIO_VIRTUAL_EN_OFFSET       0x0108U /* GPIO Virtual Enable */

#ifdef __cplusplus
}
#endif

#endif /* RK_GPIO_HW_H */